关于至简设计法的pwm仿真没有波形
在仿真时，led输出没有波形程序代码如下
module led_p(
clk,
rst_n,
led
);
input clk;
input rst_n;
output led;
regcnt_1ms,cnt_10ms;
reg led;
wire led_off,led_on;
wire add_cnt_1ms,add_cnt_10ms,end_cnt_1ms,end_cnt_10ms;
parameter TIME_1MS=6;
//计数器结构
always @(posedge clk or negedge rst_n)begin
if(rst_n==1'b0) begin
cnt_1ms <= 0;
end
else if(add_cnt_1ms) begin
if (end_cnt_1ms)
cnt_1ms<=0;
else cnt_1ms<=cnt_1ms+1;
end
end
assign add_cnt_1ms=1'b1;
assign end_cnt_1ms=(add_cnt_1ms && cnt_1ms==TIME_1MS-1);
//计数器2
always @(posedge clk or negedge rst_n)
begin
if(rst_n==1'b0) begin
cnt_10ms<=0;
end
else if(add_cnt_10ms) begin
if (end_cnt_10ms)
cnt_10ms<=0;
else
cnt_10ms<=cnt_10ms+1;
end
end
assign add_cnt_10ms=end_cnt_1ms;
assign end_cnt_10ms=(add_cnt_10ms && cnt_10ms==6-1);
//功能函数led0
always @(posedge clk or negedge rst_n)
begin
if(rst_n==1'b0) begin
led<=1;
end
else if(led_on) begin
led<=0;
end
else if(led_off) begin
led<=1;
end
end
assign led_off=(add_cnt_10ms && cnt_10ms==6-1);
assign led_on=(add_cnt_10ms && cnt_10ms==3-1);
endmodule
测试代码如下
`timescale 1 ns/ 1 ns
module led_p_vlg_tst();
// constants
// general purpose registers
// test vector input registers
reg clk;
reg rst_n;
// wires
wire led;
parameter DELY=100;
always #(DELY/2) clk=~clk;
initial
begin
//forever
//#(FAST_PERIOD/2) clk=~clk;
$fsdbDumpfile("led_p_even.fsdb");
$fsdbDumpvars(0,i1);
end
initial begin
clk=0;rst_n=0;
#DELY rst_n=1;
#((DELY*20)) $finish;
end
// assign statements (if any)
led_p i1 (
// port map - connection between master ports and signals/registers
.clk(clk),
.led(led),
.rst_n(rst_n)
);
endmodule
有大哥帮帮忙吗，小弟先谢过了。
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